The present invention relates to a semiconductor device and more particularly to the structure of a pin of a circuit and a semiconductor device and a method of forming a lead pin.
A signal frequency handled by a circuit (e.g., an LSI (Large Scale Integration)) is rising each year with development of digital technologies, and a circuit (e.g., an LSI) that handles a signal whose frequency exceeds a gigahertz is known. A serial-transfer interface or the PCI (Peripheral Component Interconnect) Express, for instance, connects between circuits (e.g., LSIs) at 2.5 Gbps (maximum frequency: 1.25 GHz). Because of reduction (attenuation) of a signal whose frequency is higher than 1.0 gigahertz and instability of a waveform caused by reflection, signal transmission on a printed-circuit board becomes difficult.
Because a connection portion of a circuit (e.g., an LSI) and a printed-circuit board is open, characteristic impedance matching may be difficult. It is expected that a signal whose frequency exceeds 10 GHz will be transmitted in the future, and thus characteristic impedance matching becomes more important.
A circuit pin (e.g., an LSI lead pin) has some problems with high-frequency signal transmission. In other words, a circuit pin (e.g., an LSI lead pin) may have a mismatch characteristic impedance when used as a signal transmission line. This results from the fact that the circuit pin (e.g., the LSI lead pin) may not have a stable reference (GND) required for characteristic impedance matching.
When different transmission lines are connected such as, for example, a connection of the LSI and the printed-circuit board, an LSI and a printed-circuit board may not be connected while a constant characteristic impedance is maintained because of physical limitations on a location, difference in pattern width, and the like.
As an example of a pin with a coaxial structure that has a central conductor, an insulator, and an outer conductor in view of impedance matching, JP-A No. 2000-261121 discloses a pin grid array (PGA) type electronic part that has an annular coaxial electrode coaxially with a pin electrode via an insulating member at the pin electrode. JP-A No. 66353/1995 discloses a semiconductor device in which an external terminal of a multilayer wiring board (package board) mounting a semiconductor chip is formed with an electrically-conducting path coaxially via an insulator between a signal line and a power line and the thickness of an insulating layer is adjusted so that the impedance of the external terminal conforms to the characteristic impedance of a printed-circuit board.